89 lines
3.2 KiB
Diff
89 lines
3.2 KiB
Diff
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commit 50ef5f99bd63808b2810981d7c64c606ea05d3fc
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Author: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Tue Jan 16 11:19:51 2018 +0000
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HJ patch #4
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diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
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index 9277ba9..c682b32 100644
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--- a/gcc/config/i386/i386.c
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+++ b/gcc/config/i386/i386.c
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@@ -12042,6 +12042,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
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If CODE is 'h', pretend the reg is the 'high' byte register.
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If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
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If CODE is 'd', duplicate the operand for AVX instruction.
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+ If CODE is 'V', print naked full integer register wname without %.
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*/
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void
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@@ -12057,7 +12058,7 @@ print_reg (rtx x, int code, FILE *file)
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&& REGNO (x) != FPSR_REG
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&& REGNO (x) != FPCR_REG));
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- if (ASSEMBLER_DIALECT == ASM_ATT)
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+ if (ASSEMBLER_DIALECT == ASM_ATT && code != 'V')
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putc ('%', file);
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if (x == pc_rtx)
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@@ -12086,6 +12087,14 @@ print_reg (rtx x, int code, FILE *file)
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else
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code = GET_MODE_SIZE (GET_MODE (x));
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+ if (code == 'V')
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+ {
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+ if (GENERAL_REGNO_P (REGNO (x)))
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+ code = GET_MODE_SIZE (word_mode);
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+ else
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+ error ("'V' modifier on non-integer register");
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+ }
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+
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/* Irritatingly, AMD extended registers use different naming convention
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from the normal registers. */
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if (REX_INT_REG_P (x))
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@@ -12234,6 +12243,7 @@ get_some_local_dynamic_name (void)
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& -- print some in-use local-dynamic symbol name.
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H -- print a memory address offset by 8; used for sse high-parts
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Y -- print condition for XOP pcom* instruction.
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+ V -- print naked full integer register name without %.
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+ -- print a branch hint as 'cs' or 'ds' prefix
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; -- print a semicolon (after prefixes due to bug in older gas).
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*/
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@@ -12403,6 +12413,7 @@ print_operand (FILE *file, rtx x, int code)
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case 'x':
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case 'X':
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case 'P':
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+ case 'V':
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break;
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case 's':
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diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
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new file mode 100644
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index 0000000..211f557
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
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@@ -0,0 +1,13 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mindirect-branch=keep -fno-pic" } */
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+
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+extern void (*func_p) (void);
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+
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+void
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+foo (void)
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+{
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+ asm("call __x86_indirect_thunk_%V0" : : "a" (func_p));
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+}
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+
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+/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_eax" { target ilp32 } } } */
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+/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_rax" { target { ! ilp32 } } } } */
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diff --git a/gcc/testsuite/gcc.target/i386/ret-thunk-10.c b/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
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index 704efee..669c8c9 100644
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--- a/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
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+++ b/gcc/testsuite/gcc.target/i386/ret-thunk-10.c
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@@ -16,5 +16,5 @@ foo (void)
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/* { dg-final { scan-assembler-times {\tpause} 2 } } */
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/* { dg-final { scan-assembler-times {\tlfence} 2 } } */
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/* { dg-final { scan-assembler "push(?:l|q)\[ \t\]*_?bar" } } */
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-/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } } */
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+/* { dg-final { scan-assembler "jmp\[ \t\]*__x86_indirect_thunk" } } */
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/* { dg-final { scan-assembler "__x86_indirect_thunk:" } } */
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